SE97BTP,547【PDF 25/53 页】IC TEMP SENSOR DIMM 8HWSON

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Sheet目录46

21页 22页 23页 24页 [25页]26页 27页 28页 29页

SE97B_1

Product data sheet

Rev. 01 27 January 2010

25 of 53

NXP Semiconductors

SE97B

DDR memory module temp sensor with integrated SPD

SHMD

Shutdown Mode.

0 Temperature Sensor is active and converting (default).

1 disabled Temperature Sensor will not generate interrupts or update

the temperature data.

When shut down, the thermal sensor diode and ADC are disabled to save

power, no events will be generated. When either of the Critical Trip or Alarm

Window lock bits is set, this bit cannot be set until unlocked. However, it can

be cleared at any time. When in shutdown mode, the SE97B will still respond

to commands normally.

When coming out of shutdown, the EVENT

output remains de-asserted as a

new temperature conversion is done. Hysteresis is subtracted from the alarm

thresholds if the temperature is falling but not used if the temperature is

rising. The temperature trend will not be determined until at least two

temperature conversions are done. Since all the alarm threshold flags

(TEMP bits 13, 14, 15) are cleared with coming out of shutdown, it was

decided to only apply hysteresis to the lower alarm threshold calculations

when determining after the initial temperature conversion if the EVENT

should assert. After the second temperature conversion the direction of

temperature is known and TEMP bits 13, 14 or 15 are changed as required

and the EVENT

is asserted as required.

CTLB

Critical Trip Lock bit.

0 Critical Alarm Trip register is not locked and can be altered (default)

1 Critical Alarm Trip register settings cannot be altered

This bit is initially cleared. When set, this bit will return a 1, and remains

locked until cleared by internal Power-on reset. This bit can be written with a

single write and does not require double writes.

AWLB

Alarm Window Lock bit.

0 Upper and Lower Alarm Trip registers are not locked and can be

altered (default)

1 Upper and Lower Alarm Trip registers setting cannot be altered

This bit is initially cleared. When set, this bit will return a 1 and remains

locked until cleared by internal power-on reset. This bit can be written with a

single write and does not require double writes.

CEVNT

Clear EVENT

(write only).

0 no effect (default)

1 clears active EVENT

in Interrupt mode. Writing to this register has no

effect in Comparator mode.

If SMBUS[0] is a logic 0, the SMBus Alert Response Address (ARA)

command can be sent to also clear the EVENT

output. When read, this

ESTAT

EVENT

Status (read only).

0 EVENT

output condition is not being asserted by this device (default)

1 EVENT

output pin is being asserted by this device due to Alarm

Window or Critical Trip condition

The actual event causing the event can be determined from the Read

Temperature register. Interrupt Events can be cleared by writing to the Clear

EVENT

bit (CEVNT) or SMBus Alert Response. Writing to this bit will have

no effect.

Table 13. Configuration register (address 01h) bit description &continued

Bit

Symbol

Description

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